(1) Field of the Invention
The present invention relates to the fabrication of semiconductor integrated circuits, and more particularly to methods of forming improved interconnections and landing pad structures in semiconductor integrated circuits.
(2) Desciption of Prior Art
Polysilicon, or poly, landing pads are used, in ultra large-scale integration technology, as interconnections between upper level conducting media and the substrate. An important feature of landing pads, as they are conventionally fabricated, is that they conserve area and thus provide for smaller device geometries. This results because poly landing pads are self-aligned contacts. Making high-reliability electrical contact between metallization layers and semiconductor regions is a problem often encountered in integrated circuit processing. In particular, contacts between aluminum and diffused regions of silicon substrates pose extreme reliability risks because of the affinity of aluminum and silicon toward interdiffusion when in contact. A barrier layer can readily be incorporated in a poly landing pad to alleviate the aluminum-silicon interdiffusion problems.
Several methods have been disclosed for forming poly landing pads with a barrier which also facilitate small cell area. In U.S. Pat. No. 5,633,196 to Zamanian, the landing pad preferably comprises a silicide layer disposed over a barrier layer which is disposed over a polysilicon layer. The barrier layer could be a refractory metal, and the order, silicide over barrier, is not essential; barrier over silicide is also preferred. U.S. Pat. No. 5,719,071 to Miller et. al. provides a method of forming a poly landing pad which comprises a tungsten layer disposed over a polysilicon layer and has the additional property of being a good etch stop. A common feature of conventional methods of fabricating poly landing pads is that the different layers are in series, so that diffusing species cannot circumvent the barrier layer.
Poly landing pads are widely used in integrated circuit devices. U.S. Pat. No. 5,036,378 to Lu et. al. discloses a memory device that incorporates a poly landing pad to facilitate small cell size. Interlevel electrical connections are provided by poly landing pads in a memory device disclosed in U.S. Pat. No. 5,198,683 to Sivan. U.S. Pat. No. 5,298,792 to Manning shows a method of forming bi-level poly landing pads. A method of constructing an integrated circuit utilizing poly landing pads is described in U.S. Pat. No. 5,477,074.
A common problem of conventional poly landing pads is that they often exhibit high electrical resistance. Resistances higher than 10,000 ohms have been measured. High resistance limits the design tolerance on circuit speed, gives rise to excessive power consumption and causes circuits to be outside of wafer acceptance test specifications. Thus high resistance curtails the usefulness of poly landing pads.
A conventional poly landing pad in a typical application is shown in FIG. 1A Prior Art. Referring to the figure, an opening is formed in a first interlevel dielectric layer 18 exposing a doped region of a silicon substrate 10. This doped region electrically connects transistors 12 and 12a as well as acting as the source of one and the drain of the other. A poly landing pad comprises at least a polysilicon layer 14 deposited in the opening in contact with the doped region. Layer 16 represents other layers of the poly landing pad, which could comprise a barrier layer disposed over a polysilicon layer; or a composite layer disposed over a polysilicon layer, with the constituent layers of the composite layer disposed over each other; or layer 16 may not be there. In the application shown in FIG. 1A Prior Art, contact is made to the upper surface of the poly landing pad, through an opening formed in a second interlevel dielectric layer 20, by conductors 22 situated over second dielectric layer 20.
The channel resistance is about 1000 ohms per micron channel length as given in C. Y. Chang and S. M. Sze, ULSI Technology, McGraw-Hill, New York, 1996, page 376. With feature sizes below 0.3 microns, channel resistances are about 300 ohms or less. It is thus important that the resistance associated with the poly landing pad be substantially less than 300 ohms for feature sizes 0.3 microns and below, if performance is not to be impaired.
The specific contact resistance of a metal to highly doped silicon may reach about 10 E-7 ohms-cm2 as a lower limit, in practice etch residues and damage may cause values 10 to 100 times larger to be observed; Chang and Sze, op. cit. pages 376-377. Metal to metal specific contact resistance is less than about 10 E-8 ohms-cm2; Chang and Sze, op. cit. page 376. Wolf; in Silicon Processing For The ULSI Era, vol. 2, Lattice Press, Sunset Press, Sunset Beach, Calif., page 253; provides data which implies a polysilicon to crystalline silicon specific contact resistance of about 6.times.10 E-7 ohms-cm2. Chang and Sze; op. cit. page 255; indicate that polysilicon resistivities are usually greater than 4.times.10 E-3 ohm-cm. Metal resistivities are typically less than 10 E-5 ohm-cm.
Using the above values of resistivity and specific contact resistance, estimates of poly landing pad resistance are readily made once its geometry is specified. For 0.3 micron feature size, the shape can be taken to be a figure of revolution with a radius of 0.3 micron at the upper surface tapering down to a radius of 0.15 microns at the lower surface. The height of the poly landing pad can be taken to be 1.0 micron and barrier or other metal layers can be taken to be 0.1 micron.
The layers of a conventional poly landing pad are in series, so the resistance of the pad is the sum of the bulk and contact resistances of the layers. When a poly landing pad, with no metal layers and with pad dimensions and properties as cited above, connects a diffused region of the substrate to an upper polysilicon layer, its resistance will be about 1132 ohms ; unless contract resistances are increased by contamination or damage, in which case much higher values can be observed. In the same situation, except that a metal layer is disposed over the polysilicon in the pad, the resistance, in absence of contamination, is increased to about 1191 ohms. If the connection is to an upper metallic conductor, the resistance of the poly landing pad with no metallic layers is about 1165 ohms and with a metallic layer the resistance is about 1159 ohms. Contamination could result in much larger pad resistances, and, in fact, resistances are observed in the range of 10 E 4 ohms. Even the lowest values to be expected of a conventional poly landing pad is in excess of 1000 ohms, which is more than three times the channel resistance, 300 ohms; certainly large enough to lead to significant reductions in performance.
Another interconnection method that is relevant to the present invention is the plug, represented in FIG. 1B Prior Art. As depicted, the plug conductor connects a diffused substrate region with conductors disposed above tie second dielectric layer. A reliable connection cannot be accomplished by depositing the upper level conductor directly into the contact opening at the same time it is deposited over the second dielectric layer because the step coverage would be too low. However, at small feature sizes, such as 0.3 microns and below, the aspect ratio is about six or higher and at such high aspect ratios even the plug reliability cannot be guaranteed. An additional disadvantage of a conventional plug is shown in FIG. 1B Prior Art; the spacing between transistors, denoted dplug, is required to be larger for a conventional plug interconnection than the corresponding spacing when a poly landing pad is used. This is because poly landing pads are self-aligned contacts.